{"id":23,"date":"2023-08-12T04:32:36","date_gmt":"2023-08-12T04:32:36","guid":{"rendered":"https:\/\/nocoffei.com\/?page_id=23"},"modified":"2023-09-17T16:41:58","modified_gmt":"2023-09-17T16:41:58","slug":"itanic-part-1-running-a-dead-architecture-on-modern-hardware","status":"publish","type":"post","link":"https:\/\/nocoffei.com\/?p=23","title":{"rendered":"Itanic, part 1\u2014 running a dead architecture on modern hardware"},"content":{"rendered":"\n

Let\u2019s embark on a tale back to the era of yore, when smartphones not yet ruled the earth, Pentiums were king, and Intel believed that x86 had no future.<\/p>\n\n\n\n

I wasn\u2019t much into technology at the time Itanium came out, so I only properly heard of it years later. Sometime in late 2021, I was introduced to Raymond Chens Old New Thing<\/a> article series on the subject. I was instantly hooked. In March 2022, I started a thorough investigation of what I could accomplish with this knowledge.<\/p>\n\n\n\n

If You Were Around When Itanium Was A Thing<\/h2>\n\n\n\n

Please skip to the end of this article and read the section \u201cStay Tuned\u201d, and keep it in mind as you read this article.<\/p>\n\n\n\n

Anything you can do, I can do more of (at the same time)<\/h2>\n\n\n\n

There are two ways to make a series of sequential tasks faster\u2013 do each one quicker, or do multiple in parallel. Operations continue to get faster and faster (by way of clock speed increases and general optimizations), but if you have a string of instructions, how do you make them work in parallel?<\/p>\n\n\n\n

\"An<\/figure>\n\n\n\n

Todays computers do what\u2019s called Out of Order\/Superscalar execution. The idea is, most execution streams that appear<\/em> linear aren\u2019t necessarily dependent on each other. You might notice that the calculation of e<\/code> and f<\/code> aren\u2019t actually dependent on each other\u2013 you load a<\/code> and b<\/code> to calculate e<\/code>, and c<\/code> and d<\/code> to calculate f<\/code>. So that\u2019s what modern computers do\u2013 they look ahead in the instruction stream and figure out what needs to be done, then analyze data dependencies, re-order the independent instructions, and finally execute those independent streams in parallel.<\/p>\n\n\n\n

\"An<\/figure>\n\n\n\n

Sound complicated? That\u2019s because it is. These principles work, but they didn\u2019t exist at all in the 90s, when Itanium was being developed. At the time, Intel had a very different idea of what parallel execution would look like\u2026<\/p>\n\n\n\n

\"Example<\/figure>\n\n\n\n

Instructions of Itanium are always grouped into blocks of three, called \u201cbundles\u201d. Each bundle has a \u201ctemplate\u201d that defines what each instruction in the bundle looks like (for example, MII means the bundle has one Memory instruction and two Integer instructions.) Bundles are executed in parallel, unless the bundle encodes a \u201cstop\u201d (denoted as ;;<\/code>) which denotes that the next instruction in the bundle is dependent on the previous instructions in the bundle. As long as no stops are present, the CPU can continue dispatching bundles in parallel, making a fully parallelized \u201cinstruction group\u201d. For instance, the original Itanium 2 can dispatch up to six instructions (two bundles) in parallel if there are no stops.<\/p>\n\n\n\n

\"Image<\/figure>\n\n\n\n
\"Image
The Itanium instruction format and examples of templates that fit into them. The white bars indicate stops. Taken from the Intel\u00ae Itanium\u00ae Architecture Software Developer\u2019s Manual Volume 3: Intel\u00ae Itanium\u00ae Instruction Set Reference, Chapter 4.<\/em><\/figcaption><\/figure>\n\n\n\n
\n
\n

Notice that this is much<\/em> less work for the silicon of the device. The compiler<\/em> is the entity responsible for generating parallelism. So instead of carefully analyzing and tracking instructions while they\u2019re in flight, the CPU just has to do dumb execution of the program, knowing that it\u2019s getting massive speedups by executing code in parallel!<\/p>\n

Now I must point out that Itanium and its ideas were a failure. This should be obvious, given that it required significant introduction. It struggled to take off in the server space early on, then AMDs 64-bit extensions to x86 killed off any remaining chance of success it had. More importantly, however, the fundamental idea of Itanium\u2013 parallel instruction decoding\u2013 does not work<\/em>. There are two main reasons for this:<\/p>\n

    \n
  1. It\u2019s not always possible to fit instructions into groupings of three. Notice that the code I wrote above, which simply calculates two numbers, had to have \u201cno-ops\u201d inserted to make a complete bundle. That\u2019s both because dependencies between instructions had to be accounted for, and because the number of templates is very limited (there are only 32) so even if parallelism could be present it may not always be possible to encode it as such. Compare this to other architectures, which have none of these limitations\u2013 just write instructions and you\u2019re set.If it seems that this is a contrived example meant to forcibly showcase the issue, let\u2019s take a look at the first instructions found in an objdump<\/code> of libc:<\/li>\n<\/ol>\n<\/div>\n<\/main><\/div>\n\n\n\n
    000000000002e580 <.plt>:\n   2e580:    0b 10 00 1c 00 21   [MMI]       mov r2=r14;;\n   2e586:    e0 60 28 63 4a 00               addl r14=1218700,r2\n   2e58c:    00 00 04 00                     nop.i 0x0;;\n   2e590:    0b 80 20 1c 18 14   [MMI]       ld8 r16=[r14],8;;\n   2e596:    10 41 38 30 28 00               ld8 r17=[r14],8\n   2e59c:    00 00 04 00                     nop.i 0x0;;\n   2e5a0:    11 08 00 1c 18 10   [MIB]       ld8 r1=[r14]\n   2e5a6:    60 88 04 80 03 00               mov b6=r17\n   2e5ac:    60 00 80 00                     br.few b6;;\n   2e5b0:    11 78 00 00 00 24   [MIB]       mov r15=0\n   2e5b6:    00 00 00 02 00 00               nop.i 0x0\n   2e5bc:    d0 ff ff 48                     br.few 2e580 <__h_errno@@GLIBC_PRIVATE+0x2e50c>;;\n   2e5c0:    11 78 04 00 00 24   [MIB]       mov r15=1\n   2e5c6:    00 00 00 02 00 00               nop.i 0x0\n   2e5cc:    c0 ff ff 48                     br.few 2e580 <__h_errno@@GLIBC_PRIVATE+0x2e50c>;;<\/code><\/pre>\n\n\n\n
      \n
    1. Cache hierarchies. With a multi-core, multi-process, modern operating system computing environment, it\u2019s practically impossible to know how physically close your data is to your execution unit.<\/li>\n<\/ol>\n\n\n\n